2 nm process

In semiconductor manufacturing, the 2 nm process is the MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node. The term "2 nanometer", or alternatively "20 angstrom" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers. As such, 2 nm is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous 3 nm node generation. TSMC began risk production of its 2 nm process in July 2024, and entered volume production in the fourth quarter of 2025 as planned. Samsung began mass production of its first-generation 2 nm (SF2) process in 2025, initially for its Exynos 2600 processor, with reported yields in the 50–60% range into early 2026. The company plans to ramp its second-generation 2 nm (SF2P) process in 2026. Intel did not pursue a conventional 2 nm node and instead advanced its Intel 18A (1.8 nm-class) process, which entered high-volume manufacturing in late 2025 and is being positioned for both internal and external foundry customers.