High Bandwidth Memory

High Bandwidth Memory (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM), initially developed by Samsung, AMD and SK Hynix. It is often used in conjunction with performance-oriented graphics accelerators, network devices, FPGAs and ASICs; some CPUs use HBM as on-package cache or RAM, such as the NEC SX-Aurora TSUBASA and Fujitsu A64FX. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices shipped with HBM were the AMD Fiji GPUs in 2015. HBM was adopted by JEDEC as an industry standard in October 2013. The second generation, HBM2, was accepted by JEDEC in January 2016. JEDEC officially announced the HBM3 standard on January 27, 2022, and the HBM4 standard in April 2025. In 2025, the world's largest manufacturers of HBM include SK Hynix, Samsung Electronics, and Micron Technology. TSMC produces the base die for HBM and is planned to be the foundry for several HBM companies in 2026. HBM has had an unprecedented demand increase, and in general DRAM (DDR4, DDR, and flash memory/NAND) price has in early 2026 "experienced compounded increases, some exceeding 200%, since early 2025 ... [because of] unprecedented demand coming from the AI sector ... HBM is crowding out commodity DRAM capacity. Micron noted a 3-to-1 conversion ratio between HBM and DDR5 wafer capacity, meaning every HBM ramp directly compresses general-purpose memory supply."