3 nm process

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In semiconductor manufacturing, the "3 nm process" is the next die shrink after the "5 nm" MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. South Korean chipmaker Samsung started shipping its "3 nm" gate all around (GAA) process, named 3GAA, in mid-2022. On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its "3 nm" semiconductor node (N3) was underway with good yields. An enhanced "3 nm" chip process called "N3E" may have started production in 2023. American manufacturer Intel planned to start "3 nm" production in 2023. Samsung's "3 nm" process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's 3 nm process still uses FinFET (fin field-effect transistor) technology, despite TSMC developing GAAFET transistors. Specifically, Samsung planned to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor). Intel's process (dubbed "Intel 3", without the "nm" suffix) would use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography, and power and area improvement. The term "3 nanometer" has no direct relation to any actual physical feature (such as gate length, metal pitch, or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a "3 nm" node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers. However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers (foundries) to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and...